Logic Synthesis, 5 op

Core content

• Main phases in implementing a digital circuit.
• Basics of VHDL language and how it is synthesized into circuit.
• Component verification and reuse. Principles of RTL simulators.
• Systems with multiple clock signals. Synchronization interfaces.

Complementary knowledge

• System realization in FPGA.
• Tri-state logic. Latches.
  
• Data sheets